The present invention relates to a method of forming an electrical connection between a stack capacitor and a node location of a substrate, particularly to a method of forming a contact pedestal for an electrical connection between a stack capacitor and a node location of a substrate.
With the memory cell density of DRAMs being continuously upgraded, a challenge to maintain sufficiently high storage capacitance subject to decreasing cell area is inevitably faced by related industries, i.e., the enhancement of storage capacitance per unit of cell area has been widely anticipated, and plenty of effort has been made to achieve it through cell structure techniques. Among such techniques are methods for forming a non-buried bit line construction (or referred to as xe2x80x9ccapacitor-under-bit-linexe2x80x9d) where a stack capacitor is electrically connected to a cell FET through a contact pedestal.
A prior art of forming such a non-buried bit line construction is disclosed in U.S. Pat. No. 6,083,831. The prior art, as represented by FIGS. 1xcx9c5, is characterized by a method of forming a contact pedestal including sidewall spacers 42 over which a stack capacitor is formed to electrically connect a node location 26 of a FET in a substrate 12 through the contact pedestal, wherein the method comprises the following steps: etching a contact opening 32 (in FIG. 2) into the insulating dielectric material 30 formed over the node location 26 to a degree insufficient to expose the node location 26; providing a spacer layer 40 (in FIG. 3) over the insulating layer 30 and into the contact opening 32 in a way that the thickness of the spacer layer 40 in the contact opening 32 is insufficient to fill the contact opening 32; anisotropically etching the spacer layer 40 to form a side spacer 42 (in FIG. 4) within the contact opening 32; etching through the contact opening 32 to expose the node location 26; filling the contact opening 32 with electrically conductive material (not shown in FIGS. 1xcx9c5); rendering the sidewall spacer 42 electrically conductive; and etching the electrically conductive material to form a contact pedestal including the sidewall spacer 42. The above steps which are required for the prior art are not always realistic or easily implemented under each of various circumstances. For example, the step of forming a spacer layer 40 over the insulating layer 30 and into the contact opening 32 in a way that the thickness of the spacer layer 40 in the contact opening 32 is insufficient to fill the contact opening 32, and the step of rendering the sidewall spacer 42 electrically conductive, are not always easy to implement under each of various circumstances. The present invention is thus developed to provide more alternatives for related industries to better or easily adapt relevant production processes to a variety of manufacturing conditions.
An object of the present invention is to simplify the process of forming an electrical connection between a stack capacitor and a node location of a substrate.
Another object of the present invention is to minimize the cost of forming an electrical connection between a stack capacitor and a node location of a substrate.
A further object of the present invention is to raise the stability of controlling the specification or quality of electrical connection formed between a stack capacitor and a node location of a substrate.
The present invention is characterized by providing methods of forming a contact pedestal in the shape of a stud for an electrical connection between a node location of a FET in a substrate, and a stack capacitor spaced from the substrate by dielectric material, wherein the methods provided by the present invention may feature the following steps: depositing a mask layer over the dielectric material; patterning the mask layer to obtain a first opening thereof; etching the dielectric material toward the node location through the first opening until the thickness of the dielectric material left over the node location is in a specified range including only the dimensions larger than zero, i.e., the thickness of the dielectric material left over the node location is larger than zero; patterning the mask layer to expand the first opening for forming a second opening thereof which is wider than the first opening; etching the dielectric material through the second opening to expose the node location, thereby forming a stud hole with a first end thereof at the node location, and with a second end thereof having a widest cross section relative to all the other parts of the stud hole; removing said mask layer; filling the stud hole with electrically conductive material to form a contact pedestal; and forming a stack capacitor structure which is at the second end of the stud hole and is electrically connected to the node location through the contact pedestal. Here the dielectric material may include an insulating layer over the node location, and a dielectric layer over the insulating layer; and the step of filling the stud hole with electrically conductive material may include the steps of: depositing the electrically conductive material to fill the stud hole; and removing the electrically conductive material which is outside the stud hole.
The methods provided by the present invention for forming a contact pedestal in the shape of a stud for such an electrical connection may also feature the following steps: forming dielectric material over the node location; depositing a mask layer over the dielectric material; patterning the mask layer to obtain a first opening thereof; etching the dielectric material toward the node location through the first opening until the thickness of the dielectric material left over the node location is in a specified range; expanding the first opening to obtain a second opening thereof which is wider than the first opening; etching the dielectric material through the second opening to expose the node location, thereby forming a stud hole with a first end thereof at the node location, and with a second end thereof having a widest cross section relative to all the other parts of the stud hole; depositing electrically conductive material to fill the stud hole for forming a contact pedestal; removing the mask layer and the electrically conductive material which is outside the contact pedestal; and forming a stack capacitor structure adjacent to the second end of the stud hole and is electrically connected to the node location through the contact pedestal.
The methods provided by the present invention for forming a contact pedestal in the shape of a stud for such an electrical connection may further feature the following steps: forming dielectric material over the node location; depositing a mask layer over the dielectric material; patterning the mask layer to obtain a first opening thereof; etching the dielectric material toward the node location through the first opening until the thickness of the dielectric material left over the node location is approximately equal to a specified dimension; expanding the first opening to obtain a second opening thereof which is wider than the first opening; etching the dielectric material through the second opening to expose the node location, thereby forming a stud hole with a first end thereof contacting the node location, and with a second end thereof having a depth approximately equal to the specified dimension, and having a widest cross section relative to all the other parts of the stud hole; depositing electrically conductive material to fill the stud hole for forming a contact pedestal; removing the mask layer and the electrically conductive material which is outside the contact pedestal; and forming a stack capacitor structure adjacent to the second end of the stud hole and is electrically connected to the node location through the contact pedestal.
It can be seen that the art provided by the present invention for forming a contact pedestal for such an application is substantially different from the prior art, and is easier implemented, while capable of offering the same function as did the prior art. For example, the present invention requires no steps such as providing a spacer layer over the insulating layer and into the contact opening in a way that the thickness of the spacer layer in the contact opening is insufficient to fill the contact opening, and rendering the sidewall spacer electrically conductive. These two steps are indispensable according the prior art and are not always easy to implement under each of various circumstances. It can thus be understood that the method provided by the present invention for forming an electrical connection between a stack capacitor and a node location of a substrate is relatively economical, reliable, and simple or systematic.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which: